1. Field of the Invention
The present invention relates to a method for fabricating a nonvolatile memory, and more especially, to a method for fabricating high density shallow trench contactless nonvolatile memories.
2. Description of the Prior Art
Nonvolatile memories, including mask- read-only memories (Mask ROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM or E.sup.2 PROM) and flash memories, retain their memory data whenever the power is turned off, and have wide applications in the computer and electronic industry. In recent years, the portable computers and telecommunications market develop rapidly and become a major driving force in semiconductor integrated circuit's design and technology. As stated by A. Bergemont, et al., in "Low Voltage NVG.TM.: A New High Performance 3 V/5 V Flash Technology for Portable Computing and Telecommunications Application" (in IEEE Trans. Electron Devices Vol. 43, p. 1510, 1996), it creates a great need for low power, high density, and electrically re-writable nonvolatile memories. That is, the memories programmable and erasable as EPROM, E.sup.2 PROM or flash memories are required for aforementioned systems to store operating systems or applications software. The basic storage cell of these programmable and erasable memories contain a double polysilicon storage transistor with a floating gate isolated in silicon dioxide and capacitively coupled to a second control gate which is stacked above it. The E.sup.2 PROM cell further comprises an access, or select, transistor. These memories execute the program and erasure by charging or discharging their floating gates. For example, the EPROM is programmed by hot electron injection at the drain to selectively charge the floating gate and erased by discharging the floating gate with ultraviolet light or X-ray, which the latter has never been commercially applied for this purpose. The E.sup.2 PROM and most of the flash memories are programmed by hot electron injection or cold electron tunneling named Flower-Nordheim tunneling, and erased mostly by Flower-Nordheim tunneling from the floating gate to the source, with the control gate ground. Herein the Flower-Nordheim tunneling, or cold electron tunneling, is a quantum-mechanical effect, which allows the electrons to pass through the energy barrier at the silicon-silicon dioxide interface at a lower energy than required to pass over it.
H. Shirai, et al., developed a method for fabricating 256 Mbit Flash memories with self-aligned, hemispherical grained polysilicon floating gate in their paper "A 0.54 .mu.m.sup.2 Self-Aligned, HSG Floating Gate Cell (SAHF Cell) for 256 Mbit Flash Memories" (in IEDM Tech. Dig. Vol. 95, p. 653, 1995). In this work, the hemispherical grained (HSG) polysilicon is applied to a floating gate to extend the upper surface area and double that of the floating gate in comparison with the conventional one. And, a high capacitive-coupling ratio of 0.8 and buried N+ diffusion layer which are self-aligned to the floating gate silicon, are realized. With contactless array and Flower-Nordheim program/erase scheme, a cell structure for achieving a high density and low power flash memory is proposed.
On the other hand, to achieve high density means to decrease the device dimensions, and it is accompanied with the problem of the short channel effect. The short channel effect may affect the electrical performance due to the reduction and degradation of the threshold voltage, that in turn increase the subthreshold current level and power dissipation. P. H. Bricout, et al., suggest in their article titled "Short-Channel Effect Immunity and Current Capability of Sub-0.1-Micron MOSFET's Using a Recessed Channel" in IEEE Trans. Electron Devices, Vol. 43, p. 1251, 1996, that the recessed channel structure nearly keeps the same threshold voltage for all channel length. This behavior is attribute to a "coupling" of the potential barrier created at both corners at the recessed floating gate. Due to this corner effect, the short channel effect can be suppressed by the appropriate geometry of the interface of the recessed channel. In addition, for equal noise margin, it is possible to use a lower concentration than in planar devices, and thus the degradation of the current device capability is limited. Furthermore, because the nonequilibrium transport is mainly located in the drain region, the magnitude of the hot carrier phenomena should be reduced compared to planar one.